EXTENSION OF MICROINSTRUCTION FORMAT IN COMPOSITIONAL MICROPROGRAM CONTROL UNIT WITH ELEMENTARIZATION OF OPERATIONAL LINEAR CHAINS

The modification of synthesis method of compositional microprogram control units is directed to decrease of hardware amount in scheme of control unit in FPGA basis. Reduction of complexity of block of microinstruction addressing is reached due to of field with pseudoequivalent operational linear chain class code. Conditions of proposed method usage possibility are given. The example of method implementation is shown.


INTRODUCTION
Modern industrial production requires cheap, secure and productive devices as results of design process.That's why reduces of the complexity of developing systems causes the topicality of hardware reduction problem in digital circuits [1].It is necessary to take into account peculiarities of device structural scheme and element basis features.Some of the peculiarities, that can be used, are pseudoequivalent states and linear type of control algorithm [2].
Compositional microprogram control unit (CMCU) is reasonable to use in case of linear (percentage of operational vertices is over 75 %) algorithms realization [2].FPGA (Field-Programmable Gate Arrays) basis is widely used nowadays for realization of control unit circuit [3,4].Problem of hardware amount minimization is solved by decrease in complexity of device main structural elements by means of decrease in main interconnections widths [5].One of ways of this problem solving is proposed in the article: control unit realization as compositional microprogram one with code sharing and elementarization of operational linear chains (OLC).
The main purpose of investigation is simplification of combinational part of CMCU via implementation in the microinstruction format of additional field containing pseudoequivalent operational linear chain (POLC) class code.The main task of investigation is development of CMCU synthesis method modification that let decrease number of LUT-elements in Block of Microinstruction Addressing (BMA).Control algorithms are represented as graph-schemes (GSA).

MAIN STATEMENTS
Graph-scheme of control algorithm consists of operational and conditional vertices, making sets E 1 and E 2 accordingly, and the set of arcs E. Let us begin vertex be marked as b 0 , end -b E .Operational vertex contain set of microinstructions where is the set of output signals of control unit.Conditional vertex contains one elements of the logical conditions set In case of operational vertices percentage is over 75 % from total number of vertices, we talk about linear GSA.
OLC is a sequence of operational vertices of graphscheme of algorithm.Each OLC α g has accidental number of inputs and only one output Q g .Formal definitions of OLC, its input and output one can find in [4].OLC with only one input and one output is called elementary OLC, outputs of which are connected with the input of the same vertex are called pseudoequivalent operational linear chains (POLC).Such OLCs make the class B i .All classes are packed into the set of POLC classes.
Let GSA contains G elementary OLC α g that form the set C.
(1) bits are enough for encoding elements of the set C. Number of components in OLC α g is marked as F g .

Maximum length
of linear chain Code sharing is obtaining of the address A q as concatenation of OLC code and its component code.
Structure of compositional microprogram control unit with elementary OLC and code sharing can be used for interpretation of graph-scheme of control algorithm (Fig. 1).Let us call this structure U 1 .
Block of microinstruction addressing in CMCU scheme realized function of memory excitation for register RG: (4) When signal Start is coming initial microprogram address is loaded into RG, zero value is loaded into CT, and flip-flop TF is set to "1" that allows reading microinstructions from control memory.There are two additional internal signals: y 0 and y E .In case of content of CT is incremented and next vertex of current operational linear chain is addressed.If then OLC output is reached and BMA prepares address of next OLC using code of current POLC class.Signal y E is used at the end of microprogram to reset flip-flop TF.The value "0" of TF output stops access to CM.
Asynchronous reset of counter must be controlled by function Signal ensures loading zero value to the CT when transition to another OLC performed.
Number of terms in BMA scheme can be decreased by implementation OLC code transformer into POLC class codes [2].But such realization demands extra FPGA recourses.
In the article complexity of code transformer is proposed to decrease by using free recourses of embedded memory.

MAIN IDEA OF PROPOSED METHOD
In initial GSA the set C 1 contains OLC α g , which are not connected to the end vertex of GSA.All operational ). = In ( 5) I is number of POLC classes.Let control memory of CMCU is realized on blocks of embedded memory with t output pins.Using unitary method of microinstructions encoding [2] we need (6) bits in appropriate field, where and constant 2 take into account internal signals y 0 and y E .So, R 4 bits of the microinstruction may be free, where takes place, a field FB with the code of POLC class can be included into microinstruction format.Structure U 2 is obtained (Fig. 2).
In CMCU U 2 variables where is bits of code K(B i ).Block of microinstruction addressing performed function ( 9) Other blocks of CMCU U 2 perform corresponding functions to functions of CMCU U 1 blocks.Let us point out that structural elements BMA, CT, RG, TF is realized in LUT-elements, and CM is implemented in embedded memory.
The following method of CMCU U 2 synthesis is proposed in this article: 1. Construction of the sets C, C 1 , and Π C for a GSA Γ.
2. Encoding of OLC, their components and classes 3. Construction of the content of control memory.4. Construction of CMCU transition table and Ψ = functions.5. Synthesis of CMCU logic circuit.

EXAMPLE OF METHOD USING
Let GSA Γ 1 (Fig. Let us encode OLC and their components in arbitrary manner (3).Addresse A(b q ) of CMCU U 2 (Γ 1 ) microinstruction are shown in Table 1.Here and after symbol U i (Γ j ) means, that CMCU U i interprets GSA Γ j .
From Table 1 one can obtain addresses, for example: and so on.
Codes of classes are set as …, Microinstruction format of CMCU U 2 includes fields y 0 , y E , FY, FB, where field FY contains Let GSA Γ 1 includes different microoperation y n , and memory blocks with output are used for realization of control memory in FPGA basis [6,7].In this case formula (7) gives us free bits.Because of usage of proposed method is possible.So, in example Contents of CMCU U 2 (Γ 1 ) control memory is shown in Table 2.

If vertex
is not an output of current OLC in memory cell with address A(b q ) microoperation y 0 is written.In opposite case in FB field of this cell code K(B i ) is written, where If vertex is connected with the end of GS A than in memory cell with address A(b q ) internal microoperation y E is written.
Transitions from outputs of OLC are expressed by next system of formulae [2]: (10) Such system is the base for CMCU U 2 transition table formation.This table consists of next columns: B i , K(B i ), b q , A(b q ), X h , Ψ h , h.Their purpose became clear from Table 3.

Addresses of microinstruction is taken from Table 1. Let us point out, that system of memory excitation functions Ψ includes functions
Total number of rows H 2 (Γ j ) in transition table of CMCU U 2 (Γ j ) is equal to number of terms in system transition formulae.In our example, H 2 (Γ 1 ) = 6.
System ( 9) is formed according to transition table.Fragments of system Ψ can be found from Table 3: (11) For minimization of terms number in ( 9) classes may be encoded with the help of EXPRESSO algorithm, for example.
Realization of logical circuit of CMCU U 2 reduces to implementation of system (9) in base of integrated circuit (FPGA) and realization of control memory on blocks of embedded or external memory.Modern CAD systems or methods [1, 2] cam be used for this purpose.

CONCLUSIONS
Proposed method of microinstruction format extension for compositional microprogram control unit is oriented to LUT-elements decrease in the block of microinstruction addressing.Number of memory blocks in device and its working time are the same as for base structure CMCU U 1 with code sharing.
Disadvantage of proposed method is in its usage limitation (8).
Term number decrease in memory excitation functions can lead to decrease number of circuit levels in combinational part of devide, that can increase speed of work.
Scientific novelty of proposed method modification is in usage of POLC classes and free recourses of control memory for LUT-elements number decrease in block of microinstruction addressing.Practical meaning is in chip parameters decrease.It allows realization of device with less cost.

Fig. 1 .Fig. 2 .
Fig. 1.Structure of compositional microprogram control unit with elementary OLC and code sharing 3) be characterized by next sets: -elementary OLC, OLC without connection to the end vertex, Π C = -classes of pseudoequivalent operational linear elementary chains, where Number of OLC bits from the set are enough for their encoding.Maximum length of OLC is let us use variables from the set for OLC components encoding.Total number of operational vertices is this number demands bit of address in CM.For encoding classes of POLC bits are used.