LUT BASED FREDKIN GATE

Context. The concept of existing computers when achieving nanoscale hardware has almost exhausted itself. This also applies to computing power and related energy costs. Reversible computing, for example billiard-ball computer, is the base model of the quantum computing which are considered to be the prospect of IT technology. Billiard-ball computing is energy-effective computing or green computing. Base of such paradigm are special logic gates. However, the mathematical apparatus for creating such computers has not yet been fully developed. The problem is that for new reversible elements that have a one-to-one correspondence between inputs and outputs, the application of well-known methods of analysis and synthesis encounters certain difficulties. So, for example, it is forbidden to use branching, which significantly complicates the synthesis. Reversible elements should provide signal transmission in the forward and reverse directions, which is in principle feasible in binary logic based on tri-states buffers, but significantly complicates the device, increases the crystal area and power consumption, which they are designed to reduce. Objective. The goal of the work is the analysis of the functionally complete reversible gates that named Toffoli gate, Fredkin gate, the analysis of the binary full adder, based on Fredkin gates and to design method for circuits based proposed gate. Methods. Analysis of the digital circuits with Boolean algebra. Synthesis digital circuits with proposed decomposition method. Design Fredkin gate in of the FPGA’s Look up Table. Simulation of proposed element in the system NI Multisim by National Instruments Electronics Workbench Group. Results. Analysis of the full adder based on Fredkin gates. Synthesis method of the reversible circuits based on Fredkin gates. LUT based Fredkin gate and it simulation. Conclusions. The conducted studies allows us to build circuits based on Fredkin gates from proposed novel elements.


ABBREVIATIONS
CNF is a Conjunctive Normal Form; DNF is a Disjunctive Normal Form; FG is a Fredkin Gate; FPGA is a Field-Programmable Gate Array; LUT is a Look up Table of FPGAs; TG is a Toffoli Gate; XOR is an exclusive OR.

NOMENCLATURE
A is a third Fredkin Gate (or Toffoli Gate) input; B is a second Fredkin Gate (or Toffoli Gate) input; C is a first Fredkin Gate (or Toffoli Gate) input; F1 is a first Fredkin Gate output; F2 is a second Fredkin Gate output; F3 is a third Fredkin Gate input; g is a "trash" output of an Adder; k is an iteration variable; p is a first input/output of an Adder; q is a second input/output of an Adder; r is a third input or input carry of an Adder; S is an additional function; 1 2 ,... n x x x are the abstract variables; INTRODUCTION Quantum computing is actual area of modern science and technology [1,2]. It is believed that quantum computers, that manipulates q-bits and q-bytes, can give a sharp leap in the memory size and computing power to solve many IT problems in the future. The area of reversible computation is closely related to these studies [3]. Reversible computation means that we can reverse calculation process and get input data, for example to check out computation. Reversible computation is the base of green computing. For example, so called "billiardball" computing get energy quants ("balls"), in contrast traditional computing, only online, so power consumption is many less. In ideal model the same balls can used many times and turn back to the source. In Quantum computer, in special quantum logic balls are q-bits, but this paradigm can be successfully used in binary logic, binary computers and digital circuit. As energy quanta in billiard computers, you can use charges stored on capacitors. In addition, it can be used for modeling in quantum devices design. Reversible computing requires novel reversible gates, for example binary gates. Some of these elements are TG, FG. Analyze and synthesis reversible gates circuits have their own characteristics and difficulties, for example fan-out problem. However, fan-out restricted allows solving race hazard problem in digital devices. Therefore, a detailed examination of these features is of considerable interest.
The object of study are the elementary Quantum gates and circuits based on binary Fredkin gates [4,5].
The purposes of the work are to analyze of the full adder based on binary Fredkin gates and design binary Fredkin gates circuits synthesis method based on proposed element, similar LUT FPGA. element is not disclosed. The first p and second q are the bits ("q-bits" in common case) to be added, the third r is the input carry (carry in). Some of the outputs (p,q) of the device repeat the inputs (p,q). There are outputs parity r p q   and carry out . rp rq pq   There is "trash" output g. Every Fredkin gate has own inputs C,B,A and outputs F1,F2,F3.
It is required: perform Boolean analyze of the FGfull adder, to propose Boolean synthesis method FGcircuit for a given logic function, perform to design LUT based FG and it simulation.
Describe every Fredkin gate input like Boolean function i i i A p q r B p q r C p q r i  . Describe every Fredkin gate output like Boolean function 1.
i i i F p q r F p q r F p q r Prove that the required parity and carry are formed at the device outputs.
Based on the analysis, to propose a synthesis method for a given logical function and verify it by completing the construction of the circuit from the end. Taking logic function It is need to design element's architecture based on LUT FPGA logic elements and to perform simulate the proposed element.
Toffoli gate TG [9], proposed in 1980, is Control-Control NOT or CCNOT. Toffoli gate's conditional symbol and functions shows Fig. 1 and Table 1.
Minimization of the Toffoli gate's function Z3 by Karnaugh map and permutation matrix shows Fig. 1.
Here C,B are control inputs (Fig.1). If C=B=1 gate works like NOT gate. Otherwise, the repeat function of A input is implemented on the Z3 output. Expressions (1) describes Toffoli gate in DNF:   Note that 3 ( 1 ) .
Minimization of the Fredkin gate's functions Z2,Z3 by Karnaugh maps and permutation matrix shows   Note that the parity is observed in Truth table Fig.4 a: the number of units is the same at the input and output, unlike Table 1. Really, in billiard logic it is impossible to change the number of balls.
Therefore in DNF and Jegalkin Form (Polinom) present expressions (2): In F3 C and not C swapped. Let S is additional Function [9]: Therefore, we can get expression (4). .
Similarly, we can prove next: .
When В=1,A=0 for F2, we get binary number 10 (NOT). Implementation of NOT operation shows expression (9): Thus, a Boolean analysis of TG and FG expressions given in the literature performed. Expressions (7), (8), (9) describes minimal functional complete sets AND,NOT (7), (9) or OR,NOT (8),(9).  We get the functions at the output of the first element (the inputs "p", 0,1 to the left of the vertical bar, the outputs F). We get the expression (10):

MATERIALS AND METHODS
So we have outputs of first gate - Fig. 6.
In terms of the Fredkin gate, it sounds like this: bits 0 and 1 are swapped places if the control signal = 1 (is set), that is, when p = 1, signal 0 appears at the output of F1.2, and at the output of F1.3 appears 1. These crosses mean "swap". Analyze of the second element shows Fig. 7.
Thus, we get Fig. 8. We see that indeed at the second output of the third element a sum or a sign of parity is formed, in fact -not parity. The control signal is the sum r p q   because it passes in transit to the output (parity). Other signals are r and . r p q   So forth element implements the following functions: DOI 10.15588/1607-3274-2020-1-5 The fifth element implements the following functions r pq rq r p r pq r p q

EXPERIMENTS
Now regard synthesis. Let we need to get circuit for next function on F2 output of the last FG: ). q r p q qr r p q r       (18) It is carry function (12). Conditional FG symbol shows Fig. 9.
q q r p q qr r p q r q q r p q qr r p q r Conversing (19) we can get expression (20): q r p q r r p q r q r p q r q r p q r q r p q r Expression (20) means, that inputs FG(k) are next: Expression (21) describes outputs of FG(k-1) too. So we have FG(k) circuit, shows at Fig. 10.
Expression (22) means, that q to the FG(k) transit from another gate: r r p q r r p q r rq p rqp rqp rq p r rq p rqp rqp rq p r q p qp r qp q p r p q r p q Expression (23)   At last, we consider q -factorization and get 4 So full circuit is shown at Fig. 14. We see that the inputs of the device are r, p, q, 0, 1 and, although we got a slightly different Fig. 5 circuit, it implements the same functions, namely a full single-bit adder. The output of the last gate F3 is not used. Output r p q   is parity (sum). It is easy to see that the circuit is reversible. For example, we can set unit values and "drive" them from inputs to outputs, using simple rules. If the input unit C is a logical unit ("ball"), then the signals installed at inputs A and B at the outputs are swapped. If there is a logical zero at input C (there is no ball), then the signals installed at inputs A and B go to the outputs without changes. Therefore, at the p=1, q=1, r=1 on outputs "parity" and "carry" are formed 1. This is forward mode. In the back mode we can install "parity"=1 and "carry"=1 and then "to roll" "balls" to the input p,q,r.
In this mode FG inputs and outputs are swapped: F1=C; F2=B; F3=A. 5 RESULTS Based on the above studies, is proposed FG realization by1-LUT (Fig. 15). 6 DISCUSSION Proposed LUT for one variable has two trees in different to usual LUT FPGA [18]. Two NOT gates on C input are needed to restore binary signal from another gates. Output F1 repeat control input C. Input B can be connected to the output F2 if C=0 or to the output F3 if C=1. Input A can be connected to the output F3 if C=0 or to the output F2 if C=1. NOT gates on input B, C and NOT gates on outputs F2, F3 are needed to restore binary signal from another gates too.
So there is bijective reflection CBA to F1F2F3 accordingly Truth Table 2. Such useful feature allows checking out gates in fault tolerant devices [19][20][21]. This implementation requires 16 transistors.
As it evident from the Fig. 15,16 -this gate works in one mode "Forward" from the left to right. If we modify circuit Fig. 15 and include "Back" mode, we shall get Fig. 17. Complexity of modified gate is very larger: 24 (NOT gates) +16 (pass transistors) = 40 transistors. Therefore, we must find new ways two modes realization, for example by tri-states buffers; however, it increase time delay yet more and power consumption too.
Next discussion direction is using proposed gate in future CMOS adiabatic logic: how to control "balls" of power supply for the NOT gates? In addition, there is the problem of capacitors power supply leaking.
Creating of the fault tolerant reversible logic may be solve in view including redundancy [21][22] with considering restriction [23].

CONCLUSIONS
The problem of creating reversible logic gates and reversible circuits and devices is the point of growing modern IT. Boolean algebra allows to describe reversible logic analyses and synthesis, but complexity such math requires to design new more simply description in terms "swap" or "not swap" relate each variable.
The scientific novelty of obtained results is that the proposed synthesis method and proposed gates creates base for design reversible circuits.
The practical significance of obtained results lies in the fact that the simulation of the proposed gates confirmed their effectiveness, which allows you to create reversible systems in FPGAs.
Prospects for further research are to study the problem of checking out and diagnosis of gates. Optimization of the amount repeaters for the fan-out imitation is interest direction. Design layout of the proposed gate may be subject of the next article. Design software for automatic synthesis proposed FG circuits may be subject of the new science projects.