DESIGN TIMED FSM WITH VHDL MOORE PATTERN

Context. The relevance of the work consists in the development of computer-aided design methods for automatic real-time logic control devices by developing a single template in a synthesized subset of the hardware description language in the style of automata-based programming with implementation on the PLD hardware platform (FPGA, CPLD). Development of the description template for timed control finite state machines (FSM) in the hardware description language VHDL, automated synthesis and implementation of the model in PLD (FPGAs, CPLDs) using


ABBREVIATIONS
ASM is an algorithmic state machine; C is a programming language; CAD is a computer-aided design system; CLK is a synchronization signal; CPLD is a complex programmable logic device; DD is a digital device; FPGA is a field-programmable gate array; FSM is a finite state machine; HDL is a hardware description language; ModelSim is a software tool produced by Mentor Graphics; PLD is a programmable logic device; RTL is a register transfer level; SD is a state diagram; TB is a testbench; ТО is the timeout; ТFSM is a timed finite state machine; VHDL is a very high speed integrated circuits HDL; UUT is a unit under test; Xilinx ISE (Integrated Synthesis Environment) is a software tool produced by Xilinx.n is the number of states of the FSM; m is number of output variables; l is maximum number of clock cycles for implementing output signals in the indicated state of the FSM;

NOMENCLATURE
t to (a i ) is a timeout; t dj (a i ) is a output delays; с 1 is the lower limit of timing constraints in FSM clocks; с 2 is the upper limit of indicated constraints; t 0 is beginning of timing constraints' "window"; t 1 is ending of timing constraints' "window" ; X iset of Onn, St, Btn; Y set of R1, YRG, YGR, G1, R2, G2; R1, YRG, YGR, G1, R2, G2 are elements of a set of Y; Onn, St, Btn are elements of a set of X; On is a signal to turn on the traffic light and start the night cycle; St is a signal to start the daytime traffic cycle; Btn is signal to turn on the green light on a pedestrian crossing; R1 is a signal to turn on red light on a main road; G1 is a signal to turn on green light on a main road; YRG is a signal to turn on yellow light on a main road (on transition R -G); YGR is a signal to turn on yellow on the main road (on transition G -R); R2 is a signal to turn on red light on a pedestrian crossing; G2 is a signal to turn on green light on a pedestrian crossing.

INTRODUCTION
Among the whole set of control systems, a significant part is logic control systems, in which control signals take logic zero or one depending on the boundary values of physical quantities that determine these parameters.For the technical implementation of these systems, the most suitable model is a structural FSM, and the state diagram is a visual representation of the functioning algorithm.A distinctive feature of finite state machines in logic control systems is the presence among input values not only signals of the control object, but also external, to the controlled system, events of the external world, which ensure the interaction of the logic control system with the external environment.
Control finite state machine operate in machine time, which is determined by the clock cycles of the FSM.But most real logic control systems interact with the outside world in metric time, i.e. they are real-time systems in which the resulting action (activity) depends not only on the logic values of the control signals, but also on the time during which these actions are performed.For their implementation, it is customary to use the model of timed FSM, which, through the implementation of timing parameters in machine time, allows taking into account the influence of the metric time on transitions between the technical states of the controlled system.
Any local digital DD that implements an information processing or control algorithm can be implemented in two ways: hardware or software-hardware.During hardware implementation, a given algorithm is described in HDL and synthesized by tools of CAD systems in PLD.The advantage of this approach is the hardware flexibility (the ability to implement any algorithm) and sufficiently large speed.When describing the functionality of DD for logic control in CAD, one of constructing styles of the HDL code structure is automata-based programming style, and it is customary to use the so-called FSM template to correctly represent HDL models of control FSM from the point of circuit synthesis.Features of the con-struction of these templates affect synthesis results of automatic logic control devices using CAD for PLD.
Thus, the task of developing single template in the hardware description language for describing automatic real-time logic control devices in the style of automatabased programming with their implementation on PLD hardware platform (FPGA, CPLD) becomes urgent.
The research object in this work is the process of computer-aided design of control FSMs in logical control systems.The research subject is the design method of VHDL models for timed control Moore FSM, their synthesis and implementation in FPGA.
The aim of this work is to develop patterns for description of timed control FSM in the hardware description language VHDL, automated synthesis and implementation of the obtained model in PLDs (FPGA, CPLD) using Xilinx ISE and subsequent analysis of the resulting circuit implementation for compliance with values of timing parameters of the circuit after implementation.

PROBLEM STATEMENT
Let Moore timed FSM model was represented as ) ), ( ( . The visual formalism of the model specification for the designed timed FSM is a temporal state diagram and a timing diagram (waveform).The temporal state diagram defines a list of input variables, output variables and FSM states, as well as delays and timing constraints, i.e. is a complete mathematical model of a timed FSM.Waveform reflects the functioning law of the controlled device in FSM time.
For the Moore FSM model it is necessary to develop a pattern of the VHDL model using style of automata-based programming, implement it using the example of building a VHDL model of the control FSM in a traffic light control system, and confirm the correctness of the proposed model by simulation, synthesis and implementation in PLD by CAD tools XILINX ISE.
The quality criterion for the obtained VHDL model is the coincidence of simulation results of the control FSM postimplementation model with the timing diagram which is specified in the specification.

REVIEW OF THE LITERATURE
Methods of using and implementing timed FSM in realtime systems are quite developed and are widely used in the design of logic control systems.
In [1], the role and place of logic control systems in the class of reactive systems that operate on the basis of reactions to external events is defined.To describe the control part of logic control systems, finite state machines, usually Moore models are used.To describe FSM in logic control systems state diagram are used, which are not the only visual representation of FSM' functioning algorithm, but also it's a full mathematical model.The designing method of automata-based logic control systems which takes into account real time and processing of external events is given.
In the classic work [2], to describe the behavior of reactive systems, it is proposed to use state charts that extend standard state diagrams.To describe the time, during which system stays in a certain state, the upper and lower time boundaries of being in the state and the concept of timeout, defined as delay in the implementation of transition to new state, were introduced.To describe the output control signals, the concept of action is introduced, the lifetime of which is ideally zero, and activity, which is performed for a certain period of time, determined by special events start and stop.
The concept of timed FSM, is a way of describing realtime systems, as introduced in [3,4].The state diagram of the FSM is supplemented by finite set of timers that take real values.Nodes of the diagram are called positions, and the edges are called transitions.Each timer is reset to zero at the time of transition and increases its value with each FSM' cycle.Each transition is associated with clock constraint, which means that this transition can only be carried out if the current timer values satisfy this restriction.Each position has a timer' constraint called an invariant; the system can be in this position only as long as its invariant is satisfied.
In [5], formal testing methods are studied that take into account timing characteristics of the system.To describe the behavior of the system, the model of TFSM was used, where instead of many timers, one timed variable is introduced.Each transition between TFSM' states is characterized by the time (delay) during which will be completed.To test TFSM, the concept of timed trace, as a sequence of transitions between states and the time during which they were performed, is introduced.The algorithm for generating a complete set of tests that allows checking whether the model matches the specified timing parameters is proposed.In [6], the TFSM model is extended due to the introduction of timeout in the state and delay -during the transition, which makes it possible to take into account more accurately timing parameters during testing timed FSM by constructing timed traces, starting from the initial state.
When constructing tests for timed FSM, the TFSM model, which takes into account timeouts in states and delays of output signals with respect to the implementation of state transition, is considered in [7].At the same time, it is taken into account that if no input signal is received during the timeout, then the FSM switches to the next state.
In general, the timed FSM model includes three types of timing parameters: timeout in states, time limit on receiving input signals, and an input signal processing time, i.e. delay of the output signal relative to the input.Moreover, timed FSM with a smaller number of parameters can be considered [8,9,10].In these works, minimization problems of timed FSM, checking their equivalence, and creation of tests are considered.
In [11], different design methods for digital controllers that implement real-time systems on different technological platforms, including programmable logic and microcontrollers, were proposed.To implement control algorithms, it was proposed to use different mathematical approaches, including UML diagrams, hardware description languages for finite state machine models, and Petri nets for describing microcontroller devices.
During creation of software models of logic control devices, the automata-based programming style is widely used [12].The essence of automata-based programming is to separate the description of device's behavior logic from the description of its output signals.Automata-based programs are strictly structured and they have three types of functions: transition functions, output functions, and functions for assigning a new state, which take into account time delays.Automata-based programs are also strictly stereotyped using multi-position selection operators (switch, case) and conditional operators (if, elsif -else) in the C programming language.
The method for implementing models of timed FSM in the VHDL language was proposed in [13].To implement delays in the states of the Moore FSM, it is proposed to use loops in states and a special variable count, which decreases by 1 in each FSM cycle, which corresponds to a sync pulse.In terms of implementing the structure of the HDL model, it is proposed to use a single-process template.Results of behavioral simulation of traffic lights were presented.
Three categories of state machines were introduced in [14]: regular (simple) state machines, timed state machines, and recursive state machines.For these categories of machines, different templates of HDL models in the VHDL and Verilog languages are presented, as well as the results of their simulation in the ModelSim system (from Mentor Graphics) and synthesis using ISE (from Xilinx).
When analyzing timing parameters of the designed digital devices based on FPGA, the developer has the opportunity to conduct timing simulation at the following stages: after creating the initial project description (Simulate Behavioral VHDL Model); after performing synthesis and translation (Simulate Post-Translate VHDL Model); after the phase of mapping the logic description of the project to the physical resources of the crystal (Simulate Post-Map VHDL Model); after completion of the placement and tracing procedures (Simulate Post-Place & Route VHDL Model) [15].Such organization allows to detect possible errors at the earlier stage of design, and thereby to avoid significant time losses.

MATERIALS AND METHODS
During description of real-time control systems' behavior, it is necessary to take into account time aspects of their behavior.For this, the state machine model is expanded by introducing a timed variable, and the concept of timed FSM is introduced.Logic control devices, built on the basis of timed FSM, operate in machine time, that are measured in FSM cycles, that is, discrete periods of time during which the machine passes from one state to another.The duration of the FSM cycle in real devices, as a rule, is determined by the clock Clk.Based on this timed variables are also measured in FSM cycles.
As a rule, three parameters are used to describe time aspects in timed FSM model: timing constraints t c , (incoming) timeouts t to , and output delays td, which are sometimes called output timeouts [10].The input timeout determines the maximum waiting time for the input event for each state of the FSM.If input signal didn't came during timeout, then FSM start a survey of the input variables and go to another state.Timing constraints are intervals at transitions that limit the time during which a transition can be completed.Output delays (output timeouts) reflect the time taken by the FSM to complete the transition, i.e, the output signal will appear on the output after a time interval during which the transition is completed, which is determined by the output delay.
In logic control systems, the concept of «input values» is divided into input actions and events.Events along with input variables provide the interaction of the control FSM with the external environment.Input actions are implemented by FSM by interrogation of input variables in accordance with the algorithm of its operation in the control cycle, and events are realized instantly and lead to a change in the state of the FSM.
Depending on the purpose and features of using models of timed control FSM, there are many modifications of such models that take into account both the method of processing events and the method of processing delays in the implementation of transitions and output signals of the FSM.
Based on features of the functioning of logic control systems, a model of a structural timed FSM was proposed in [16].It can be represented by nine W is a set of In general, a timed FSM can contain all three timing parameters, but for a specific task, timed machines with one or two of these parameters can be used.
Timed FSM model, which consists of three timing parameters < t c , t to , t d > cannot be directly attributed to the traditional Moore model.Its output function is similar to the Moore FSM, but the output signal is formed taking into account the delay, but not during FSM' transition to a new state.The time of appearance (change) of output signals is tied to the working edge of the clock signal.In the proposed model of a timed FSM, the logic of its operation is as follows.
When the FSM goes into the current state a i , the main timing parameter t to (a i ) is determined for it, i.e., the time during which the FSM must be in the current state, if an external event ahead of time transfers the machine to another state.t to is detected in FSM cycles.After the time t to has elapsed, the FSM responds to the input signals (interrogates them) and goes to the next state.
Output signals of the FSM in the current state a i appear at outputs at the moment determined by t dj (a i ), that is, by output delays for signals y j in the state a i .For each of the output signals y j , its delay is determined in FSM cycles and can be different.At t dj (a i ) = 0, the model of timed FSM approaches the classical Moore model.
Processing external events is as follows.For each state a i , input constraints t c (a i ) are set, that is, the period of time during which the FSM, in state a i , can process incoming events.Timing constraints are determined in FSM cycles and calculated as t c = (t 1 -t 0 ).For t 1 =  and t 0 =0, timed FSM without input timing constraints is considered.If an external event occurred outside of the timing constraints' "window", the FSM does not respond to it.
To describe a timed FSM, a temporal state diagram is used, which is represented in the form of FSM template in the hardware description language.To implement the Moore FSM model with a single timed variable, which is represented in the hardware description language, it is proposed to use an additional counter count, which is used to count the number of FSM cycles during which the FSM implements certain timing parameters.When the timed FSM makes a transition to a new state, the value of this counter is reset to 0. In a two-process VHDL template, the assignment of the new state and the new value of the counter occur in one process which is associated with the formation of the synchronous sequential part of the FSM.The VHDL code of the synchronization process, the assignment of the new state and the new counter value are shown in Listing It should be noted that in the second process, which describes the combinational part of the FSM, it is necessary to add next_count <= ( others => '0' ); after the standard when others => next_state <= a1;.It is important.
Let's consider implementation approach of the three aforementioned timing parameters in the VHDL hardware description language, namely, incoming timeouts, timing constraints on events processing, output delays.
The ТО i timeout is realized by a multiple transition from state to the same state, wherein the number of transitions determined by the number of FSM timeout cycle.The value of the counter is compared with ТО i -1, since during transition to а i state, the FSM will stay there during one cycle until the count will be checked and that the timeout would be equal exactly to ТО i cycles, then ТО i -1 cycles must be repeated.That is, in the temporal state diagram, the state timeout is implemented using loops, conditions for which are checks of counter signal value.Fig. 1 shows a graphical representation of the Moore FSM state with timeout ТО i and timing diagram of this timeout implementation.
A fragment of the VHDL-code of timeout implementation for state a1 is shown in Listing  Timing constraints t c , during which the processing of external events in the indicated state of the FSM is allowed, are defined as t c = [c l , c 2 ].To implement the time limit, it is necessary to compare the value of the counter signal with the lower and upper bounds of the corresponding time limit c l .Let's consider the lower time limit c l .The counter value is compared with c l -1, since during transition to state а i , FSM stays there during one clock cycle until the count will be checked and so that the lower boundary corresponds exactly to c l clocks, it is necessary more c 1 -1 clock cycles during which FSM will stay in this state.Similarly, in the last cycle, in which event processing is enabled, the counter value is compared with c 2 -1.
Fig. 2 presents conditions of the transition by an external event (Btn), taking into account timing constraints, and timing diagram of the process for external event processing under the condition t c = [2,5].The event triggers on the third FSM clock.A fragment of the VHDL-code of event processing in the state a 1 is shown in listing  For the hardware implementation of output delays, it is necessary that values of the output signals of the Moore FSM depend not only on the current state, but also on the current value of the counter, which determines the delay of the output signal from the moment when FSM moves to the corresponding state.Fig. 3 shows the implementation of the initial delay during d 1 FSM clock cycles (d 1 =2) for signal y 1 in the form of state diagram and timing diagram.Note that the output signal in the VHDL model of the Moore FSM is realized using a conditional signal assignment statement outside process.y1 <= '1' when ( state = a1 and count >= d1 ).
To implement the VHDL-model of the timed FSM, it is proposed to use a two-process template: one process to describe sequential part of the FSM and second process to describe transition function and counting function of FSM clock cycles.

EXPERIMENTS
To test the proposed method of VHDL-models formation of timed FSM, let's consider a traffic light control system on a pedestrian crossing.
Let's consider the functioning algorithm of the traffic light, which operates in two modes: daytime and night.
The set of input signals X a set of Onn, St, Btn, Onn.Thus, Onn and St are actions, and Btn is an event.
The set of output signals for traffic lights Y is a set of R1, YRG, YGR, G1, R2, G2.Note that G R  .The interface of the traffic light control system is shown in Fig. 4. -state a 2 -yellow when changing (G-R), outputs {YGR, R1, R2}, delay to 2 ; -state a 3 -red on a road, green on a pedestrian crossing, outputs {R1, G2}, delay to 3 ; -state a 4 -yellow when changing (R-G), outputs {YRG, R1, R2}, delay to 2 ; -state a 5 -green on a road, red on a pedestrian crossing, outputs {G1, R2}, delay to 3 ; -state a 6 -switching to green on a pedestrian crossing and red on a road by button Btn, delay to 6 , outputs {R1, G2} with delay of the appearance t d , delay in the state to 6 ; -state a 7 -only yellow is on, delay is to 1 .
The traffic light algorithm is as follows.When the control device is turned on (Onn = 1), the night cycle of the traffic light starts, yellow light flashes on the main road (а 1 -а 7 ), the traffic light on a pedestrian crossing does not work.After starting the daytime cycle (St = 1) the transition' system (а 2 -а 3 -а 4 -а 5 -а 2 ) is implemented.At state a 5 , when on a main road green light is on, reception "window" t c for external event Btn is defined (pressing the jump button).When this event is processed, the control FSM go to state a 6 .At the same time, on a main road red light is turned on, but red light is held up on a pedestrian crossing, and green is turned on with a delay t d (time to prepare for crossing).During the period t c , only one signal (external event) Btn can be received.
Thus, for traffic control system temporal state diagram of timed Moore FSM can be built (Fig. 5).
Fig. 6 shows the timing diagram of Moore FSM for traffic light control system in the daytime cycle of the work, which is essentially is specification of the designed device.

RESULTS
To confirm the reliability of obtained results, a twoprocess VHDL-model of the timed Moore control FSM was developed for the traffic light control system without putting the counter into a separate process.A fragment of the two-process VHDL-model is shown in listing 4.
All delays described in a separate package, which fragment is represented in the listing 5.
For verification of the presented model, as well as for synthesis and implementation, the Xilinx ISE 14.7 system was used.Behavioral and post-implementation simulations for initial description were performed on the CPLD XC9572XL-10-TQ100 (Post-Fit Simulation) and on the FPGA XC3S500E-5fg320 (Post-Place & Route Simulation).The clk period for simulation is 100 ns.Synthesis report of the latch-triggers absence was analyzed.Timing diagram of behavioral simulation, which illustrates a fragment associated with reaction to event B tn , is shown in the Fig. 7.
Switching delay is 0 ns.Single short-term pulses do not occur.Thus, when implementing the device on FPGA and CPLD, its operation must comply with the original description (specification).
As a result of the synthesis of the device on the FPGA XC3S500E-5fg320 and CPLD XC9572XL-10-TQ100, CAD tool identified an FSM with 7 states, which codes are the same for both chips.
The expected minimum number of triggers is 9: 3 triggers for encoding 7 states, 6 triggers for the counter (since the maximum timeout is to 3 = 45).RTL schematic report for both chips confirmed this.However, in the synthesis report for FPGA, 11 triggers appear, 2 of which are used due to the peculiarities of the technological implementation of the RTL circuit on FPGA, which is confirmed by the report in the technology schematic format.Latch triggers are absent in the report.To implement functions of transitions and outputs, combinational circuits were synthesized.218 combinational elements were synthesized on the XC9572XL-10-TQ100, and 69 combinational elements -on the XC3S500E-5fg320.Table 1 shows some totals from the synthesis report.For FPGA: minimum Clk period: 5.700 ns (Maximum Frequency: 175.434MHz).

DISCUSSION
The usage of Moore FSM models with timing delays is traditional for description logic control systems and has been worked out in sufficient detail for control programs in C language [1,12].Models of abstract timed FSMs with timeouts, timing constraints, and output delays are widely used in testing of timing parameters of microcontroller control systems and telecommunication protocols [5][6][7][8][9][10].On the other hand, in [13][14][15], hardware implementations of timed FSM models in CAD tool using hardware description languages were proposed.But pro-posed FSM model' templates in hardware description languages did not take into account all parameters.
In this work, an attempt to define templates of language structures in VHDL for timed Moore control FSMs with the possibility of processing events, which are external to the control system, was made.Experiments' results of the synthesis of circuit implementations for timed control FSMs in PLDs confirmed that synthesizers in CAD tools (in particular, Xilinx ISE) interpret different language constructs of VHDL differently from the point of timing parameters implementation, although results of behavioral simulation for them coincide with specifica-tion.On the example of simulation (after implementation) for circuit implementation on PLD of control FSM in logic control system, elements of the HDL template are proposed to use that correctly implement timing parameters defined in the specification.
The direction of further research may be the construction of HDL templates for models of timed event-driven FSM in logic control systems and test verification of these models.

CONCLUSIONS
The method for constructing a HDL description for real-time systems, which can be synthesized into a programmable logic device, was developed in the work.
Models of real-time systems, such as a state diagram, a timed FSM with many timers, a timed FSM with one timer, an extended timed FSM, a timed FSM with timeouts and timing constraints were considered in this work.Based on these models, a complete structural model of timed Moore FSM was proposed.
Features of hardware and software-hardware approaches of real-time systems' realization were analyzed.A method for using an additional counter to store the value of a timed variable and implementation of timed parameters during usage of hardware approach based on the structural model of a timed Moore FSM, were proposed.
An algorithm of the traffic light operation was analyzed.Based on this algorithm, the temporal Moore state diagram was developed for the traffic light control system.Based on the temporal state diagram, a two-process VHDL-model of the timed Moore FSM (without moving the counter to a separate process), was proposed and developed.
Verification, synthesis and implementation of the developed VHDL model using Xilinx ISE environment were performed.Synthesis and simulation before and after implementation was performed for CPLD XC9572XL-10-TQ100 and FPGA XC3S500E-5fg320.Synthesis and simulation results of the circuit after implementation confirm the operability and correctness of the developed VHDL model.
The scientific novelty of the work lies in the definition of the method for constructing the HDL description of real-time system, a characteristic feature of which is the synthesis of the description into a programmable logic device, which allows to increase the speed of developed devices by increasing the development time of the inputoutput interface.

Figure 1 -
Figure 1 -Implementation of the timeout in the state of the Moore FSM

Figure 2 -
Figure 2 -Implementation of timing constraints and events' processing

Figure 3 -
Figure 3 -Implementation of output delays for signal y 1

Figure 4 -
Figure 4 -Traffic light control system interface Let's define states of the control FSM: -state a 1 -turning on the FSM, there are no output signals, delay to 1 ;-state a 2 -yellow when changing (G-R), outputs {YGR, R1, R2}, delay to 2 ;-state a 3 -red on a road, green on a pedestrian crossing, outputs {R1, G2}, delay to 3 ;-state a 4 -yellow when changing (R-G), outputs {YRG, R1, R2}, delay to 2 ;-state a 5 -green on a road, red on a pedestrian crossing, outputs {G1, R2}, delay to 3 ;-state a 6 -switching to green on a pedestrian crossing and red on a road by button Btn, delay to 6 , outputs {R1, G2} with delay of the appearance t d , delay in the state to 6 ;-state a 7 -only yellow is on, delay is to 1 .The traffic light algorithm is as follows.When the control device is turned on (Onn = 1), the night cycle of the traffic light starts, yellow light flashes on the main road (а 1 -а 7 ), the traffic light on a pedestrian crossing does not work.After starting the daytime cycle (St = 1)

Figure 5 -Figure 6 -
Figure 5 -State diagram of the Moore timed FSM for traffic light control system

Figure 7 -Figure 8 -Figure 9 -
Figure 7 -Behavioral simulation of reaction to event Btn X set of input signals, с T set of timed variables for timing constraints on each arc of the state diagram; сi t is an сi-th element of a set of   C X set of input signals from the control object; E X set of external events; c Y set of reactions (control signals), F Y iset of activities (initial functions); g is output function; 0 z is code of the initial state of the FSM; n is number of arcs in the state diagram; p is maximum number of constraints on transitions to the і-th node of the state diagram in the event processing mode; k is corresponds exclusively to the transition event function; toi t is timeout for each state; 1. Listing 1. VHDL code of the formation process of the FSM sequential part process (Clk, Reset) begin if Rst = '1' then state <= a1; count <= ( others => '0' ); elsif rising_edge(Clk) then state <= next_state; count <= next_count; end if; end process; 2. 3.