SYNTHESIS OF THE FINITE STATE MACHINE WITH DATAPATH OF TRANSITIONS ACCORDING TO THE OPERATIONAL TABLE OF TRANSITIONS

Context. The problem of formalizing the description of a microprogram finite state machine based on the principle of operational transformation of state codes with the help of a modified transition table is considered. The object of research was a model of a microprogram finite state machine with datapath of transitions. Objective. The goal of the work is development and research of a method for formally specifying a microprogram finite state machine with datapath of transitions in the form of a modified table of transitions containing sufficient information for synthesizing the logic circuit of the finite state machine in the basis of programmable logic devices. Method. A new way of representing the formal solution of the problem of algebraic synthesis of a microprogram finite state machine with datapath of transitions in the form of an operational table of transitions is proposed. This table is a modification of the direct structural table traditionally used in the synthesis of microprogram finite state machines. The use of the previously known representation of the formal solution of the problem of algebraic synthesis in the form of a system of isomorphisms of automaton algebras is too formalized and makes it difficult to synthesize the logical circuit of the finite state machine due to the separate description of the transition and output functions. It is shown that the structure of a microprogram finite state machine with datapath of transitions requires information about the set of interpretations of state codes and the transition operations used to be entered into the traditional table of transitions. It is noted that the proposed operational table of transitions contains sufficient information for the synthesis of the logical circuit of the finite state machine. An example of constructing an operational table of transitions for a finite state machine given by a graph-scheme of the implemented control algorithm is shown. The example demonstrates various ways to interpret state codes. The procedure for synthesizing the circuit for generating codes of transition operations and the circuit for generating microoperations according to the operational table of transitions is proposed. Results. An example of the implementation of the main stages of the synthesis of a finite state machine with datapath of transitions according to the operational table of transitions is considered. Examples of synthesized finite state machine models in the VHDL language are given, which take into account the peculiarities of the representation of finite state machine models in Xilinx Vivado CAD. The results of the synthesis of the finite state machine according to VHDL models in FPGA basis are shown. Conclusions. The experiments carried out confirmed the sufficiency of the operational table of transitions for describing a microprogram finite state machine with operational transformation of state codes for the purpose of further synthesizing its logic circuit. Prospects for further research are the use of the proposed operational table of transitions in the development of various methods for the synthesis and optimization of microprogram finite state machine with operational transformation of state codes.

NOMENCLATURE a m is a current FSM state; K(a m ) is a current FSM state code; a s is a transition state; K(a s ) is a transition state code; X is a set of logic conditions; x i is an element of set X; L is a number of logic conditions (power of set X); Y is a set of microoperations; y i is an element of set Y; N is a number of microoperations (power of set Y);  h is a set of input memory functions for switching FSM memory from state a m to state a s ; h is a number of FSM transition; A is a set of FSM states; INTRODUCTION Digital systems are widely used in various fields of activity [1]. Structurally, the digital system can be considered as a combination of operational unit and control unit [2][3]. The control unit is based on a formal description of behavior and can be implemented in the form of a finite state machine model [4][5]. There are two models of finite state machines -the Mealy machine and the Moore machine [4][5]. The logic circuit of any FSM model is characterized by such parameters as hardware expenses, clock frequency and power consumption. As follows from [6], there is a direct relationship between these characteristics. Optimization of the characteristics of FSM circuits is an important scientific and practical problem, the solution of which is devoted to many scientific papers around the world [1][2][3][4][5][6][7]. One of such characteristics, which focuses on the finite state machine structure considered in this paper, is the hardware expenses of implementing the logic circuit of the FSM in a given element basis.
The object of study is the process of synthesis of the logic circuit of a finite state machine with operational transformation of state codes.
This process in the case of a canonical finite state machine is performed according to a direct structural table, which is a formal description of the behavior of the FSM and contains sufficient information for the synthesis of its circuit. In the case of operational transformation of state codes, this table requires modifications taking into account the processes of information transformation that takes place in this class of FSM.
The subject of study is the finite state machine with operational transformation of state codes, in which the transformation of state codes is carried out using a finite set of arithmetical and logical operations.
The purpose of the work is formalization of the description of the finite state machine with operational transformation of state codes in the form of the modified direct structural table.

PROBLEM STATEMENT
Suppose given finite state machine, characterized by the sets A={a 1 , ..., a M }, X={x 1 , ..., x L }, Y={y 1 , ..., y N } and implements a certain control algorithm. The synthesis of the logic circuit of the FSM provides for the implementation of the function of transitions T=T(X, T) and the function of outputs Y=Y(X, T) in the given elementary basis.
The paper solves the problem of synthesizing a finite state machine with datapath of transitions, in which the transition function T=T(T, W) depends on the code of the current state and the code of transitions operation. To solve the problem, it is necessary to develop a formalized representation of the FSM with DT, which allows the following stages of the synthesis of the logic circuit of the FSM: -synthesis of each structural blocks; -construction of VHDL description of the synthesized FSM; -FSM synthesis using Xilinx Vivado CAD using FPGA.

REVIEW OF THE LITERATURE
Various optimization methods for reducing of hardware expenses of FSM circuit are known today. Such methods include, for example, methods of structural decomposition [7]. Their use leads to FSM circuits with several levels of conversion of logic signals.
Another approach to reducing hardware amount, considered in this article, is to use the principle of operational transformation of state codes [8]. According to it, the transformation of state codes in an FSM is not carried out with the help of a canonical system of Boolean equations, but with using of a set of arithmetical and logicalal operations that form a special datapath of transitions. This structure of FSM with DT shows a fairly high efficiency in terms of hardware expenses [9].
In the work [10] considers an algebraic model of FSM with DT, according to which this FSM can be represented as a system of isomorphisms of partial algebras (transition algebras). Each transition algebra describes the rule of transformation of state codes for its subset of FSM transitions and assumes its own scalar or vector interpretation of state codes. The system of isomorphisms of algebras today is the only formal way to specify the FSM with DT. However, the synthesis of the FSM circuit directly by the system of isomorphisms of algebras is complicated due to different representations of FSM transitions.
A direct structural table is traditionally used to specify the FSM behavior [2,7]. The method of synthesis of FSM according to the table of transitions is widely known and applied in practice [7]. This article proposes a new way to specify the FSM with DT, based on a modified table of transitions.

MATERIALS AND METHODS
The canonical FSM is usually set in the form of a direct structural table (table of transitions), the format of which is presented in Fig. 1 [2]. The purpose of columns of the table of transitions and its use for the synthesis of the FSM circuit are described in [7]. Let the FSM be given in the form of a GSA G, [7], which is shown in Fig. 2, left. In the right part of Fig. 2 shows a description of GSA G in the kiss format, which is used to describe finite state machines in the test collection LGSynth93 [11]. GSA G is marked by the states of the Moore FSM, contains M = 10 states a 0 -a 9 , L = 3 input signals x 1 -x 3 , N = 4 output signals y 1 -y 4 and B = 13 FSM transitions. To encode 10 states, it is sufficient to use R = 4 binary digits.
Let's synthesize for GSA G a finite state machine with datapath of transitions. Suppose the next transitions operations O 1 -O 3 are given: (1) In operation O 1 , a decimal constant 9 is added to the current state code K(a m ). This means that a scalar decimal interpretation is used for the codes K(a m ) and K(a s ) when performing O 1   Let's perform an algebraic synthesis of FSM with DT, which is as follows: -to each state of the FSM we will match the unique four-digit binary vector having the corresponding decimal interpretation; -for each FSM transition we will match any operation from (1) -(3), which for the given state codes transforms the code K(a m ) into the code K(a s ).
The result of algebraic synthesis in graphical form is shown in Fig. 3. In each vertex, which is marked by the Moore FSM state, the state code is shown in scalar (decimal) and vector (binary) interpretations. Each FSM transition is marked by one of the operations (1) -(3): "+9", "& 1000" or " 0100". Since the operational transformation of state codes affects only the function of the FSM transitions and does not affect the function of the outputs, the microoperations in Fig. 3 are not shown, although they continue to correspond to Fig. 2.
As we can see, with the chosen values of state codes, all transitions within the GSA G are implemented using of operations (1)-(3). For example, the transition from state a 3 with code K(a 3 ) = 9 10 = 1001 2 to state a 4 with code K(a 4 ) = 2 10 = 0010 2 is performed using the operation "+9", and from the result 18 10 = 10010 2 the lower four digits 0010 2 were taken.
Let's modify the table of transitions of the canonical FSM as follows: 1. Instead of column K(a m ) add columns K 1 (a m ), K 2 (a m ), ..., K I (a m ), which correspond to all used interpretations of state codes for all I interpretations.
2. Do the same with column K(a s ), adding columns K 1 (a s ), K 2 (a s ), ..., K I (a s ) instead.
3. Add a column W h containing information about the code of transitions operation that implements current FSM transition. The values of w i specified in this column correspond to the values 1 in the binary code of the corresponding operation. Filling in this column is preceded by the step of encoding of transitions operations.
4. Remove the column  h , because the conversion of state codes in the FSM with DT is carried out using a set of transitions operations, rather than a system of canonical equations of the transition function.
Let's call the received table as the operational table of transitions (OTT). In the general case, its structure corresponds to Fig. 4.  Let's present in the form of OTT the results of algebraic synthesis of the FSM, shown in Fig. 3. To do this, we encode the given transitions operations O 1 -O 3 with unique binary codes of bit size R W =  log 2 3  = 2, which are formed by signals W = {w 1 , w 2 }. The result of coding is presented in Table 1. Taking into account the coding of transitions operations, the operational table of transitions, hich corresponds to GSA G and Fig. 3, is presented by Table 2.
In this example, the number of interpretations of the state codes I = 2 (scalar decimal value and binary vector). When using the transition operation O 1 , the code K 1 (a m ) is converted into the code K 1 (a s ); when using operations O 2 and O 3 , the code K 2 (a m ) is converted into the code K 2 (a s ). For example, the transition h = 5 is realized by operation O 1 . Therefore, in this transition, the conversion of scalar interpretations of codes is performed, i.e. the code K 1 (a m ) = 9 10 into the code K 1 (a s ) = 2 10 . This transformation is performed using the adder circuit with the preservation of four lower digits of the result.
Note that the dash in the column W h means that for the implementation of the corresponding transition, values w i = 1 are not formed, which corresponds to the code of operation O 1 (w 1 = 0, w 2 = 0).

EXPERIMENTS
Let's show an example of Table 1, that the information contained in the OTT is sufficient for the synthesis of the logic circuit of the FSM with DT. The structural model of the FSM with DT, corresponding to the Moore FSM, is shown in Fig. 5 and contains the next synthesized blocks: -the block W generates a set of signals W with digit capacity R W =  P  according to formula (4), where P is the number of transition operations; X is the set of L input signals of the FSM corresponding to the logical conditions x 1 , ..., x l of the given GSA; T -state code of the FSM with digit capacity R -the block DT corresponds to the datapath of transitions and implements a set of transitions operations in the form of a set of separate combinational circuits, the outputs of which are multiplexed by the signal W and enter the FSM memory register that is part of the DT [8]; -the block BMO corresponds to the cicruit of formation of microoperations and implements the output function of the Moore FSM in the form of a set of microoperations Y = {y 1 , ..., y n } according to formula (5) by analogy with [2,7] Let's synthesize these blocks. Under the synthesis of the logic circuit of the machine we will understand the development of VHDL-model, which can be synthesized in the element basis of Xilinx FPGA [12].

Block W
This block implements a system of Boolean equations of function (4), in which each signal wi is formed in accordance with expression (6) ) ,  T  T  T  T  x  T  T  T  T  T  T  T  T  T  T  T  T  w   x  T  T  T  T  x  T  T  T  T  T  T  T  T In the general case for the system (7) it is possible to carry out minimization in order to reduce the complexity of the circuit [4, p. 269]. System (7) can be described in VHDL in different ways, for example, as a separate process (Fig. 6) [12].
In this model, the description of the buses T, X and W corresponds to the same FSM signals and is discussed below in the description of the architecture block.
Block DT This block includes an operational part that implements operations (1) -(3) and their multiplexing, as well as a memory register designed to store the current FSM state. The functional diagram of these nodes is shown in Fig. 7. Since for the considered example the circuit of DT consists of standard functional blocks, special synthesis of this circuit is trivial and is not required.
In Fig. 8 VHDL-model of OAP, in which the operational part and the memory register are represented by separate processes, is showed.
The first process corresponds to the operational part of DT. The absence of the synchronization signal C in the list of sensitivity of the process indicates the asynchronous nature of the operation of this block. Within the process transformation of the state code T is performed using one of three transitions operations depending on the value of the operation code W. As will be shown below, for the signal T used data type "unsigned", which allows you to interpret this signal simultaneously as an unsigned integer and as a binary vector.
The second process corresponds to the memory register. Receiving data in the register, as well as the switching to the initial state 0101 2 in the presence of the Reset signal are carried out synchronously on the leading edge of the C signal.

Block BMO
The synthesis of this block is performed in accordance with the contents of column Y h of the operational table of transitions (Table 2). In this case, to obtain a synthesized VHDL model of the block, it is possible to use the method considered for block W (build a system of Boolean equations for generated microoperations), or use the case operator belonging to the synthesized subset of the VHDL language. We use the second method, as a result of which we obtain the VHDL model of the BMO block, shown in Fig. 9.
In this model, after the start of the process, all digits of the output bus Y are given zero values. Then, depending on the values of the signals on the bus T, the required discharges of the bus Y are set to 1. It is expected that state code values not provided by the case operator should not appear on the T bus. Let's combine the considered VHDL descriptions into a single object entity, resulting in a synthesized model of FSM with DT (Fig. 10). A feature of this model is the presence of the output port S, which displays the code of the current state T. This is done in order to analyze functioning of the FSM in the process of behavioral modeling.

RESULTS
Synthesis of the VHDL model shown in Fig. 10, in CAD Xilinx Vivado 2021.1 allowed to obtain hardware expenses for implementation of the FSM, equal to 7 LUTelements (based on FPGA xc7a12ticsg325-1L FPGA of Artix-7 series).
To test the correctness of VHDL model of the FSM with DT, a behavioral part was developed that implements the next functionality: -single generation of the Reset signal in the range of 10-90 ns from the beginning of the simulation; -regular signal C generation with a duration of 20 ns with an interval of 100 ns; -regular generation of input signals x 1 -x 3 with different values of lengths of 1 and 0 levels. time t = 380 ns, marked by a vertical marker, the FSM performs transition from the state with the code T = 0 (state a 2 ), analyzing value of signal x 1 . Since at this point x 1 = 1, the transition is carried out to a state with code T = 9 (state a 3 ), which is consistent with Fig. 3. After the transition to state a 3 , the formation of microoperations y 2 and y 4 is carried out, which is consistent with Fig. 2. Thus, the synthesis of FSM with DT for this example is performed correctly.

DISCUSSION
A finite state machine with datapath of transitions differs from a canonical finite state machine in that it uses a set of arithmetical and logical operations (transitions operations) to convert state codes, which form a datapath of transitions. Each transitions operation involves a certain interpretation of binary state codes and is formally specified on a set of interpreted values. One of the interpretations is a scalar representation in the form of an unsigned integer, which allows to define on the set of state codes operations of addition, subtraction, and so on. Interpretation of the state code in the form of a binary vector allows to specify over the state codes bitwise logical operations, shift operations and the others. Information about the used operations and methods of interpretation of binary state codes is necessary for the schematic implementation of the transition function of the FSM.
The input data for the synthesis of the logic circuit of the canonical FSM is a table of transitions (direct structural table), which contains information about the functions of transitions and outputs of the FSM. However, its use for FSM with DT is impossible due to the lack of information about the methods of interpretation of state codes and transitions operations. In this paper, it is proposed to use the so-called operational table of transitions for specification the FSM with DT, which provides extended information about the function of transitions of the FSM. The example considered in the paper showed that specification of the FSM with DT in the form of an operational table of transitions is sufficient for the synthesis of the logic circuit of the FSM in the form of VHDL model focused on the use element basis of FPGA-type.
The possibility of obtaining with the help of VHDL model numerical characteristics of hardware expenses for the implementation of the FSM circuit allows us to recommend the use of the operational table of transitions as a way to present the results of other known methods of hardware expenses in FSM circuit.

CONCLUSIONS
The article proposes a solution of scientific problem of formalizing the description of the processes of state codes transformation in a finite state machine with datapath of transitions, which allows to bring the description of this class of finite state machine in line with traditional description of other classes of finite state machines.
The scientific novelty of the work is to modify the direct structural table by adding to it information about al-gebraic interpretation and methods of transformation of state codes. The resulting operational table of transitions is proposed for the first time and contains sufficient information for the synthesis of the logic circuit of the FSM.
Practical use of the obtained results is possible in the development of formal methods of structural synthesis of finite state machines with operational transformation of state codes.
Prospects for further research are to develop methods of synthesis of FSM circuit, based on the formal representation of the FSM in the form of operational table of transitions.