MODELS FOR EMBEDDED REPAIRING LOGIC BLOCKS

Abstract

The goal of this article is to improve the quality and reliability of digital systems-on-chips by creating an infrastructure for embedded testing, diagnosis, optimization and repairing through the use of hardware redundancy and reduce the speed of functional operations. The models of combinational circuits, focused on solving real-world problems of embedded repairing components of the logic devices, are proposed. The logical scheme is improved by using operational and control automaton for modeling digital devices, and focused on solving practical problems of embedded repairing logic components by increasing the processing time and additional hardware costs to create wrapper of addressable elements. The proposed structures can also be used for hardware modeling functionalities of digital projects through the use of PLD, which allows significantly improving the performance of software model verification. The proposed solution of embedded repair of gates for combinational circuits makes it possible to comprehensively solve the problem of autonomous repair of digital system-on-chip through the use of time and hardware design redundancy.