DOI: https://doi.org/10.15588/1607-3274-2018-2-13

DESIGN AUTOMATION OF EASY-TESTED DIGITAL FINITE STATE MACHINES

M. A. Mіrosсhnyk, Y. V. Pakhomov, A. S. Shkil, E. N. Kulak, D. Y. Kucherenko

Abstract


Context. The relevance of the work is to provide minimal additional hardware costs during design automation of easy-tested digital
devices, which are represented by models of control finite state machines on hardware description languages.
Objective. To develop procedures of models’ constructing of easy-tested control finite state machines on hardware description
languages and estimate hardware costs for different methods of hardware redundancy introduction to HDL-models of finite state machines.
Method. The introduction to HDL-models of control finite state machines, which are presented in the form of the FSM template,
hardware redundancy (additional fragments of the HDL-code), providing the forcing setting of finite state machine into an arbitrary state
without the use of synchronizing sequences. For implementation of this approach, the method of FSM’s state table extending is applied,
which ensures the mode of bypassing of all nodes of FSM’ state diagram in the diagnostic mode.
Results. Simulation of extended VHDL-models of the control FSM using Active-HDL confirmed the operability of this approach.
Synthesis of these models using CAD XILINX ISE confirmed the receipt of testable structures and showed the minimum hardware costs for
the method associated with the extension of the state table, in comparison with the organization of the shift register in the Scan Path mode.
Conclusions. The task of computer-aided design of testable control finite state machine on the basis of application of FSM’ setting
methods into given state is solved in the work. The optimal way of the setting organization into an arbitrary state of the control FSM is to
expand the state table, which improves the controllability of FSM’ states and leads to the structure’ transformation of their HDL-models
into easy-tested ones.
The scientific novelty of the work is the transformation of control FSM’ models on hardware description languages, which is realized
by introduction of the additional symbol to the state table, providing the settings of the FSM into an arbitrary state without the use of
synchronizing sequences.
The practical significance of obtained results is to confirm the optimality, in terms of additional hardware costs, of the setting method
of the control FSM into an arbitrary state by introducing the additional symbol into the state table.

Keywords


control finite state machine; state table; shift register; scanned path; hardware description language; CAD; Active-HDL; XILINX ISE.

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