DESIGN TIMED FSM WITH VHDL MOORE PATTERN

Abstract

Context. The relevance of the work consists in the development of computer-aided design methods for automatic real-time logic control devices by developing a single template in a synthesized subset of the hardware description language in the style of automatabased programming with implementation on the PLD hardware platform (FPGA, CPLD). Development of the description template for timed control finite state machines (FSM) in the hardware description language VHDL, automated synthesis and implementation of the model in PLD (FPGAs, CPLDs) using Xilinx ISE, subsequent analysis of the received circuit implementation for compliance with values of timing parameters of the circuit after implementation.

Objective. The aim of the work is to develop principles for constructing models of timed control FSM in the VHDL hardware description language. In this work, we solved the problem of constructing a pattern for describing models of timed control Moore FSM using VHDL, automated synthesis and implementation of the obtained VHDL model in PLDs (FPGA, CPLD) using Xilinx ISE and subsequent analysis of the resulting circuit implementation for compliance with values of timing parameters of the circuit after implementation.

Method. Realization of models’ parameters of timed FSM in logical control systems using VHDL statements. Development of VHDL language constructions of timed FSM models for timing parameters implementation that provide the correct automated synthesis and implementation of these models in PLDs (FPGA, CPLD) using CAD tools Xilinx ISE.

Results. Synthesis and implementation of proposed templates of VHDL-models of timed control Moore FSM in logic control systems by XILINX ISE CAD tools confirmed the receipt of not redundant circuits in PLD (FPGA, CPLD), and simulation after implementation showed the efficiency of such models.

Conclusions. The work solves the problem of computer-aided design of timed control FSM in real-time logic control systems. To solve this problem, VHDL-models of timed control Moore FSM were developed, which made it possible to implement control FSM with time constraints, timeouts and output delays. Automated synthesis and simulation of VHDL models based on the developed templates confirmed the efficiency and correctness of the proposed models.

The scientific novelty of the work consists in the further development of methods for constructing templates of HDL models of timed control Moore FSM, which made it possible to implement control FSM with time constraints, timeouts and output delays, as well as perform their correct automated synthesis and simulation.

The practical value of results is in the development of procedures for constructing VHDL models of timed Moore control FSM in real-time logic control systems, which made it possible to automate the synthesis of control FSM taking into account the possibility of processing external events and implementing arbitrary delays for output signals and to increase the flexibility and speed of designed systems. The developed procedures can be useful for designers of timed control FSM in Xilinx ISE.