SELF-TIMED LOOK UP TABLE FOR ULAs AND FPGAs

Authors

  • S. F. Tyurin “Perm National Research Polytechnic University”, Perm, Russia. “Perm State University”, Perm, Russia.
  • A. Yu. Skornyakova “Perm Scientific-Industrial Instrument Making Company”, Perm, Russia.
  • Y. A. Stepchenkov Federal Research Center “Computer Science and Control” of the Russian Academy of Sciences, Moscow, Russia.
  • Y. G. Diachenko Federal Research Center “Computer Science and Control” of the Russian Academy of Sciences, Moscow, Russia.

DOI:

https://doi.org/10.15588/1607-3274-2021-1-4

Keywords:

Self-Timed, Lookup Table, Simulation.

Abstract

Context. Self-Timed Circuits, proposed by D. Muller on the rise of the digital era, continues to excite researchers’ minds. These circuits started with the task of improving performance by taking into account real delays. Then Self-Timed Circuits have moved into the field of green computing. At last, they are currently positioned mainly in the field of fault tolerance. There is much redundancy in Self-Timed Circuits. It is believed that Self-Timed Circuits approaches will be in demand in the nano-circuitry when a synchronous approach becomes impossible. Strictly Self-Timed Circuits check transition process completion for each gate’s output. For this, they use so-called D. Muller elements (C-elements, hysteresis flip-flops, G-flip-flops). Usually, Self-Timed Circuits are designed on Uncommitted Logic Array. Now an extensive base of Uncommitted Logic Array Self-Timed gates exists. It is believed that SelfTimed Circuits are not compatible with FPGA technology. However, attempts to create self-timed FPGAs do not stop. The article proposes a Self-Timed Lookup Table for the Self-Timed Uncommitted Logic Array and the Self-Timed FPGA, carried out either by constants or utilizing additional memory cells. Authors proposed 1,2 – Self-Timed Lookup Table and described simulation results.

Objective. The work’s goal is the analysis and design of the Strictly Self-Timed universal logic element based on Uncommitted Logic Array cells and pass-transistors circuits.

Methods. Analysis and synthesis of the Strictly Self-Timed circuits with Boolean algebra. Simulation of the proposed element in the CAD “ARC”, TRANAL program, system NI Multisim by National Instruments Electronics Workbench Group, and layout design by Microwind. The reliability theory and reliability calculations in PTC Mathcad.

Results. Authors designed, analyzed, and proved the Self-Timed Lookup Table’s workability for the Uncommitted Logic Arrays and FPGAs. Layouts of the novel logic gates are ready for manufacturing.

Conclusions. The conducted studies allow us to use proposed circuits in perspective digital devices.

Author Biographies

S. F. Tyurin , “Perm National Research Polytechnic University”, Perm, Russia. “Perm State University”, Perm, Russia.

Honored Inventor of the Russian Federation, Dr. Sc., Professor, Professor of the Automation and Telemechanic Department.

Professor of the Software Computing Systems Department.

A. Yu. Skornyakova , “Perm Scientific-Industrial Instrument Making Company”, Perm, Russia.

PhD, Design engineer of the JSC.

Y. A. Stepchenkov , Federal Research Center “Computer Science and Control” of the Russian Academy of Sciences, Moscow, Russia.

PhD, Head of the department, Institute of Informatics Problems, Federal Research Center “Computer Science and Control”.

Y. G. Diachenko, Federal Research Center “Computer Science and Control” of the Russian Academy of Sciences, Moscow, Russia.

PhD, Head of sector, Institute of Informatics Problems.

 

References

Muller D. E., Bartky W. S. A theory of asynchronous circuits, On the Theory of Switching, Part 1. Harvard, University Press, 1959, pp. 204–243.

Varshavsky V. I. Ed. Aperiodic Automata. Moscow, Nauka, 1976, 304p.

Marakhovsky V. B., Surkov A. V. Globally asynchronous system of interactive Moore state machines, IET Computers and Digital Techniques, 2016, Vol. 10, Issue 4, pp. 186–192.

eds.: Cortadella Jordi, Yakovlev Alex and Rozenberg Grzegorz GALA (Globally Asynchronous – Locally Arbitrary) Design’’, LNCS 2549, Concurrency and Hardware Design, Advances in Petri Nets. Berlin, Springer, 2002, pp. 61–107.

Yakovlev A. Energy-modulated computing, In Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, 2011, pp. 1–6.

Sokolov Danil, Khomenko Victor, Mokhov Andrey et al Automating the Design of Asynchronous Logic Control for AMS Electronics, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, Volume 39, Issue 5, pp. 952–965. DOI: 10.1109/TCAD.2019.2907905

Stepchenkov Y. A., Zakharov V. N., Rogdestvenski Y. V. et al. Speed-independent floating point coproceccor / [] // IEEE EastWest Design & Test Symposium: International, 26–29 Sept. 2015:proceedings. Batumi, Georgia, IEEE, 2015, pp. 7493110. DOI: 10.1109/EWDTS.2015.7493110

Smith S. C. Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits [Electronic resource], Available at: https://ieeexplore.ieee.org/document/4231891 DOI: 10.1109/TVLSI.2007.898726

Self-timed Circuits [Electronic resource]. Access mode: https://ocw.mit.edu/courses/electrical-engineering-andcomputer-science/6-004-computation-structures-spring2017/c7/c7s2/c7s2v5/self-timed-circuits-6-21-/

Walker A., Lala K. An Approach for Self-Timed Synchronous CMOS Circuit Design [Electronic resource], Access mode: https://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/200400681 74.pdf

Nielsen L. S., Niessen C., Sparsø J., Berkel van. C. H. Lowpower operation using self-timed circuits and adaptive scaling of the supply voltage [Electronic resource], Access mode: https://backend.orbit.dtu.dk/ws/files/4151035/Nielsen.pdf

Masashi I., Takashi N. Performance Comparison between Selftimed Circuits and Synchronous Circuits Based on the Technology Roadmap of Semiconductors [Electronic resource], Access mode: http://webhost.laas.fr/TSF/WDSN08/2ndWDSN08(LAAS)_file s/Texts/WDSN08-05-Imai.pdf

Kenny R., Watt J. The Breakthrough Advantage for FPGAs with Tri-Gate Technology [Electronic resource]. Access mode:URL:https://www.altera.com/en_US/pdfs/literature/wp/w p-01201-fpga-tri-gate-technology.pdf

Tyurin S. F. LUT based Fredkin gate, Radio Electronics, Computer Science, Control, 2020, No. 1, pp. 44–53.

Drozd A. V., Drozd M., Martynyuk O., Kuznietsov M. Improving of a Circuit Checkability and Trustworthiness of Data Processing Results in LUT-based FPGA Components of Safety-Related Systems, CEUR Workshop Proceedings, 2017, Vol. 1844, pp. 654–661.

Drozd A.V., Drozd M., Kuznietsov M. Use of Natural LUT Redundancy to Improve Trustworthiness of FPGA Design, CEUR Workshop Proceedings, 2016, Vol. 1614, pp. 322–331.

Speedster22i Configuration User Guide [Electronic resource]. – Access mode: http://www.achronix.com/wpcontent/uploads/docs/Speedster22i_Configuration_User_Guide_ UG033.pdf

Maheswaran K., Akella V. Hazard-free implementation of the self-timed cell set in a Xilinx FPGA [Electronic resource]. Access mode: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.39.42 76&rep=rep1&type=pdf

Osuna C. G., Ituero P. and López-Vallejo M. A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs) [Electronic resource]. Access mode: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC3926550/

National Instruments [Electronic resource]. Access mode: http://www.ni.com/multisim/

Microwind & Dsch Version 3.5 [Electronic resource]. Access mode: http://auto.teipir.gr/sites/default/files/microwind_manual_lite_v 35.pdf

Tyurin S. F. Investigation of a Hybrid Redundancy in the FaultTolerant Systems, Radio Electronics, Computer Science, Control, 2019, No. 2, pp. 23–33. DOI: 10.15588/1607-32742019-2-3

El-Maleh A. H., Al-Yamani A., Al-Hashimi B. M. TransistorLevel Defect Tolerant Digital System Design at the Nanoscale. Research Proposal Submitted to Internal Track Research Grant Programs [Electronic resource]. Access mode: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.474.3 844&rep=rep1&type=pdf

Mead C. A., Conway L. Introduction to VLSI Systems [Electronic resource]. Access mode: https://www.researchgate.net/publication/234388249_Introducti on_to_VLSI_systems

Downloads

Published

2021-03-24

How to Cite

Tyurin , S. F. ., Skornyakova , A. Y. ., Stepchenkov , Y. A. ., & Diachenko, . Y. G. . (2021). SELF-TIMED LOOK UP TABLE FOR ULAs AND FPGAs . Radio Electronics, Computer Science, Control, 1(1), 36–45. https://doi.org/10.15588/1607-3274-2021-1-4

Issue

Section

Radio electronics and telecommunications