TEST GENERATION AND SIMULATION FOR CROSSTALK FAULTS

Authors

  • Yu. A. Skobtsov Donetsk National Technical University, Donetsk, Ukraine, Ukraine
  • V. Yu. Skobtsov United Institute of Informatics Problems of the NAS of Belarus, Minsk, Belarus, Belarus
  • A. A. Shalyto Saint-Petersburg University of Information Technologies, Mechanics and Optics, Saint-Petersburg, Russia, Russian Federation

DOI:

https://doi.org/10.15588/1607-3274-2015-4-11

Keywords:

test generation, crosstalk faults, genetic algorithms, multi valued logic, fault simulation.

Abstract

The main models of crosstalk faults are defined: 1) induced positive and negative pulses, 2) induced delays. The purpose of the work is
to increase the effectiveness of the methods of constructing checking tests for digital systems based on an evolutionary approach and models of non-const fault. Formalized statement of the problem of test generation for a single crosstalk faults-induced pulses and delays. It is shown that this problem is reduced to solving a system of logic equations in the multi-valued alphabet. The 8-valued alphabet and multivalued functions for basic gates are defined. Simulation method was developed in the 8-valued alphabet for crosstalk faults. On this basis, the genetic algorithm is proposed for test generation of single cross-faults. The test generation problem for fault-induced delay is formalized A genetic algorithm of test generation for fault-induced is proposed. Developed algorithms and software for test generation for crosstalk faults, which improve the quality of test generation by using evolutionary techniques. The approbation of the developed methods is implemented at circuits of international catalogs ISCAS85, ISCAS89, which showed an increase in the completeness of tests by 15%.

References

Скобцов Ю. А. Моделирование, тестирование и диагностика цифровых устройств / Ю. А. Скобцов, Д. В. Сперанский, В. Ю. Скобцов : учебное пособие. – М. : Национальный от- крытый университет «ИНТУИТ», 2012. – 439 с. 2. Rubio A. An approach to the analysis and detection of crosstalk faults in digital VLSI circuits / A. Rubio, N. Itazaki, X. Xu, K. Kinoshita // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. – 1994. – Vol. 13, № 3. – P. 387–394. 3. Chen W. Y. Analytic Models for Crosstalk Delay and Pulse Analysis under Non-Ideal Inputs / W. Y. Chen, S. K. Gupta, M. A. Breuer // International Test Conference, Washington, Nov. 1997 : proceedings. – Los Alamitos : IEEE, 1997. – P. 809–818. DOI:10.1109/TEST.1997.639695. 4. Chen W. Y. Test generation for Cross-Induced Delay / W. Y. Chen, S. K. Gupta, M. A. Breuer //International Test Conference, Atlantic City, 28–30 September 1999 : proceedings. – Los Alamitos : IEEE, 1997. – P.191–200. DOI:10.1109/ TEST.1999.805609 5. Chen W. Y. Test generation for Cross-Induced Faults: Framework and computational results / W. Y. Chen, S. K. Gupta, M. A. Breuer // Journal of Electronic Testing : Theory and Applications. – 2002. – Vol. 16. – P. 17–28. 6. Krstic A. Delay Testing Considering Cross-Induced Effects / A. Krstic, J.-J. Liou, Y.-M. Jiang, K.-T. Cheng // International Test Conference, Baltimore, 30 October-01 November 2001 : proceedings. – Los Alamitos: IEEE, 2001. – P. 558–567.DOI:10.1109/TEST.2001.966674. 7. Bai X. HyAC. A Hybrid Structural SAT Based ATPG for Crosstalk / X. Bai, S. Dey, A. Krstic // International Test Conference, Washington, 30 September–2 October 2003 : proceedings. – Los Alamitos: IEEE, 2003. – P. 112–121. DOI:10.1109/ TEST.2003.1270831. 8. Arunachalam A. A Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Cicuits / A. Arunachalam, R. Arunachalam // International Conference on VLSI Design, Kolkata, 3–7 January 2005 : proceedings. – Los Alamitos: IEEE, 2005. – P. 479–484. 9. Li H. Selection of Crosstalk-induced Faults in Enhanced Delay test / H. Li, X. Li // Journal of Electronic Testing: Theory and Applications. – 2005. – Vol. 21, № 2. – P. 181–195. 10. Palit A. K. Test Pattern Generation for Crosstalk Faults in DSM chips using Mofified PODEM / A. K. Palit, K. K. Duganapalli, W. Anheier // Eectronics System integration Technology Conference, Greenwich, 1–4 September 2003 : proceedings. – Los Alamitos : IEEE, 2003. – P. 393–398. DOI:10.1109/ESTC.2008.4684311. 11. Chun S. XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults/ S. Chun, Y. Kim, M.-H. Yang, S. Kang // Asian Test Symposium, Sapporo, 23–24 November 2008 : proceedings. – Los Alamitos : IEEE, 2008. – P. 83–88. 12. Ganeshpure K. P. On ATPG for Multiple Aggressor Crosstalk Faults in Presence of Gate Delays / K. P. Ganeshpure, S. Kundu / / International Test Conference, Santa Clara, 23–25 October 2007 : proceedings. – Los Alamitos : IEEE, 2007. – P. 1–7. 13.Chary Sh. Automatic path delay test generation for combined Resistive Vias Resistive bridges and Capacitive Crosstalk delay faults / Sh. Chary, M. L. Bushnell // International conference on VLSI Design, Hyderabad, 3–7 January 2006. – Los Alamitos : IEEE, 2006. – P. 413–418. 14.Phadoongsidhi M. SCINDY: Logic Crosstalk Delay Fault Simulation in Sequential Circuits / M. Phadoongsidhi, K. K. Saluja // International Conference on VLSI Design, Kolkata, 3–7 January 2005 : proceedings. – Los Alamitos : IEEE, 2005. – P. 820–823. 15. Скобцов Ю. А. Эволюционные вычисления : учебное пособие / Ю. А. Скобцов, Д. В. Сперанский. – М. : Национальный Открытый Университет «ИНТУИТ», 2015. – 331 с.

Published

2015-06-26

How to Cite

Skobtsov, Y. A., Skobtsov, V. Y., & Shalyto, A. A. (2015). TEST GENERATION AND SIMULATION FOR CROSSTALK FAULTS. Radio Electronics, Computer Science, Control, (4). https://doi.org/10.15588/1607-3274-2015-4-11

Issue

Section

Progressive information technologies